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SDR Receiver Performance Overview

sdr receiver performance

SDR receiver performance depends on the architecture selected and the ability of the analog-to-digital converter to handle a wide range of genuine and spurious signals. 

We usually view the key elements of receiver performance as sensitivity, selectivity and dynamic range. Signals arriving at your radio usually have power ranging between -127 to -13 dBm. This represents an amplitude ratio of 500,000:1, or 0.1 to 50,000 μV. Wow! My SDR can handle that? Yes, it usually can.

Sensitive receivers hear weak signals. The weakest are measured as the Minimum Discernible Signal in a given bandwidth. Often, we specify MDS or Noise Floor around -130 dBm for CW. Gain and internal noise determine performance. However, in the real world, it’s external noise – particularly man made – that limits weak signal reception.

Once your receiver hears signals, it’s selectivity that sorts them out. We usually evaluate selectivity by the performance of bandwidth filters. With DSP, selectivity is pretty much a done deal. Unlike analog radios, SDR selectivity is just a matter of math.

Where things get interesting is dynamic range, which is about handling really strong and really weak signals at the same time. With legacy receivers, dynamic range depended on AGC. We applied Automatic Gain Control to keep components in their linear range. With SDR receiver performance, dynamic range is mostly set by the number of bits used for analog to digital conversion. The more, the better.

What is good HF SDR receiver performance? Expect dynamic range above 100 dB and a Minimum Discernible Signal of around -127 dBm. All of my SDR receivers meet the sensitivity hurdle, and the more expensive Flex and Perseus exceed this dynamic range benchmark.

SDR Receiver Performance – Dynamic Range

Engineers measure dynamic range through various techniques. In an ideal SDR, you simply measure the difference between noise floor (weakest signals) and the ADC clipping level. This is the signal to noise ratio. In numerical terms, very weak signals only use a few ADC bits. Since there is always truncation or quantization error in the least significant bit, weak signals are hampered by quantization noise.

On the other hand, a really strong signal might eventually overload the ADC. As a result, it clips, producing “all ones”. You can use amplification or attenuation to keep signals in the AGC sweet spot, except for the cheaper 8 bit devices. This sweet spot is called Blocking Dynamic Range (BDR).

A more interesting metric is Spurious Free Dynamic Range. SFDR is measured relative to the fundamental carrier (dBc) or ADC full-scale clipping level (dBFS). Most radios produce spurious signals. Spurs are unintended or artificial signals. They result from harmonics, mixing and inter-modulation products. (DSP also creates spurs. These include clock feed through and harmonics, data errors that produce discontinuities, and ADC imperfections.) When spurs have enough strength to rise above the noise floor, they interfere with desired signals. This interference lowers the dynamic range of your receiver.

You would like to see BDR above 115 dB and SFDR above 100. Both can be improved by adding more bits to the ADC.

Dynamic Range Depends on Design

Designers create dynamic range by choosing the receiver architecture and the best components. If they choose direct sampling and digital down conversion, designers eliminate most of the spurious signals that cause DR problems in traditional and QSD designs. If they choose an ADC that has low phase noise in its clock,  any dynamic range problems in SDR are more likely caused by non-linearity and passive IMD in the analog front end.

The bottom line is this. Traditional analog receivers are plagued by cumulative nonlinear effects all along the signal chain. These nonlinearities arise in both passive and active components. QSD reduces these components and their effects significantly. Direct sampling and digital down conversion eliminates them after the front end.

Performance of SDR then turns on two factors:

  • Architecture and its ability to minimize spurious responses downstream. This includes gain distribution and how well the entire system is constructed to balance spurious responses against the ADC ability to handle them.
  • The ability of the ADC to convert a wide dynamic range of signals, and includes the spectral purity of the sampling clock.

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