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SDR Receiver Architecture – Approaching Ideal

sdr receiver architecture

Architecture means “the complex or carefully designed structure of something”. Let’s look at how SDR receiver architecture has evolved over time. 

Generally, advances in SDR receiver architecture have focused on implementing more and more of a radio in digital rather than analog components. Simply put, this has involved moving the ADC (analog to digital converter) closer and closer to the antenna.

Digital signal processing and computer radio control arrived for the ham and SWL during the 1990’s. At first the focus was audio processing. Then, as affordable personal computers spread, we started using software controlled radios.

By the mid 1990’s, manufacturers started replacing final IF stages with DSP. These were mainly “mini SDR” receivers bolted on after the analog multi-conversion stages. For example, ICOM started doing 36 kHz with the 756PRO and Kenwood did 11.3 kHz digital processing in the TS-870S.

In parallel, early homebrew SDR designs involved using computer sound cards for ADC and doing signal processing, display and control in the PC. Typically these involved a Quadrature Sampling Detector with down-conversion to baseband or very low IF. The original Flex Radio design, published in QEX in 2002 and implemented as the SDR-1000 a year later, simply sent I/Q signals at 11.025 kHz to the sound card.

Later, QSD radios began to include their own ADC, and provided I/Q data over USB to the computer. My SDRPlay RSP2 is an example of a QSD receiver that does uses this approach. The invention of the Tayloe Detector in 2001 stimulated many direct-to-baseband conversion receivers. Tayloe Detectors virtually eliminated mixing conversion loss and provided great image rejection at very low cost.

Recent advances in ADC speed and performance have now enabled low cost Direct Sampling, where the analog-to-digital conversion happens much closer to the antenna. For example, the Perseus and Flex 6300 SDR receiver architectures use Direct Sampling followed by Digital Down Conversion to baseband. This gets rid of all analog components except for some front end amplification and, optionally, preselect filtering.

SDR Receiver Architecture – Benefits of Direct Sampling

With QSD architecture, image rejection depends on analog components being matched over variations in temperature, voltage and manufacturing specifications. Typically, I/Q balance is less than perfect and there are spurious signals around DC in the baseband. With Direct Sampling, amplitude and phase balance, as well as the tuning oscillator, is all implemented numerically. The results are pretty close to perfect.

Both my Perseus and Flex 6300 use the Direct Sampling architecture shown above. The ADC is close to the antenna, and runs at 80 MHz in the Perseus and 123 MHz in the Flex 6300. In this way, the entire HF spectrum is captured and converted into I/Q data up front. Since the ADC clock is running at more than twice the speed necessary to sample HF, this is called oversampling.

The Nyquist sampling theorem says that the sampling frequency must be at least twice the signal bandwidth. So, to capture and digitize the entire spectrum up to 30 MHz, the ADC must sample at least 60 million samples/second. But, if all you want is to capture a portion of the spectrum, a smaller bandpass, then you can sample at a much lower rate than the highest carrier frequency. This is called undersampling or bandpass sampling. To make this work, you need to be able to filter out the (aliased) passbands that you don’t need.

The neat thing is that if you are direct sampling using oversampling, you do not actually need front end preselect filters. We will explain more about that later.

SDR Receiver Architecture – Capturing the Benefits

There are two different benefits associated with SDR. The first is to get rid of analog components and their limitations, and just use numbers. The second is to be able to reconfigure your radio for multiple purposes using software. In the ham radio and SWL worlds, we have made great strides to capture the first set of benefits with digital processing. Not much has been done on multi-purpose reconfigure with software. That is currently falling mostly to commercial, industrial and military applications.

As for the hardware side, most receivers use Application Specific Integrated Circuits or Field Programmable Gate Arrays for implementation. ASIC is good for analog to digital conversion and down conversion. FGPA is good for filtering, because of its high speed and ability to reconfigure. You will find FGPA used from things like FFT and frequency translation. As far as much of the final DSP work, especially involving floating point or matrix operations, these tend to run best in dedicated DSP modules or indeed, general purpose computers like your PC. However, because of the very high data rates involved, the trend today is to perform all digital processing in the radio, and use a networked PC for control and display.

Will the day ever arrive where the ideal SDR is just a chip connected to an antenna? Well, for some applications, it is already here. You might want to check out the Analog Devices AD9361 RF Agile Transceiver  that covers 70 MHz to 6.0 GHz. This SDR is just a single chip. You hook it up to an antenna on one side and a baseband I/Q processor on the other. Power output 8 dBm, what you typically find used for Bluetooth.

For the time being, though, I am satisfied with my Perseus and Flex as pretty much “state of the art”.

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