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Coding My SDR Core Receiver

sdr core receiver

Here are the basic building blocks for my SDR Core Receiver. Lots of math to turn signal data into sounds that make sense.

Last week, I described my latest project to develop a new SDR receiver which handles two channel diversity reception. My goal is to include an ability to record and playback two synchronized channels of I/Q data.

While I need to write drivers to interface with my two-channel receivers, once this front end is complete I just need a single channel SDR. The design of my SDR core receiver is shown above.

Basically, you need five components to sequentially process each block of samples arriving from the radio hardware. First is your ability to tune anywhere within the bandwidth chunk provided by the radio. This Local Tune section (in red) is basically a complex software oscillator acting on the complex data samples coming in.

Second, your SDR core receiver must Decimate (lime) or reduce the volume of data down to a manageable level. I have chosen 25,000 samples per second as my standard processing rate for the rest of the DSP. So, with a 1 MHz bandwidth, I need to decimate by 40, for example.

Next, you need a proper bandwidth Filter (purple) for your desired mode. This might be 6 kHz for AM, 2.3 kHz for SSB or 0.5 kHz for CW, and so on. I have found this component works best in the frequency domain, so some FFT is required.

SDR Core Receiver – Marching On

Once the desired signal has been filtered down to 25,000 samples per second, it’s easy for you to apply a Digital AGC (blue) component to level things out. Then, finally you need to Demodulate (orange) your signals and turn them into audio.

I will start by demodulating for AM, AMS, SSW and CW.

Along the journey, various data buffers will be provided for subsequent visual display such as spectrum and waterfall, etc. Also, I can bolt on more components for noise reduction and audio filtering as we go along.

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